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AM79C973 pcnet?- fast iii hardware users manual
? 1999 advanced micro devices, inc. advanced micro devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repr esentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- ?cations and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or othe rwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, ?tness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. trademarks copyright ? 1999 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. auto-poll, magic packet, and pcnet are trademarks of advanced micro devices, inc. product names used in this publication are for identi?cation purposes only and may be trademarks of their respective companies.
i table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 chapter 2 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.1 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.2 ethernet node controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.3 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.4 ethernet interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.5 expansion boot rom/flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.6 lan wake-up through the pme pin . . . . . . . . . . . . . . . . . . . . . .2-2 2.7 serial eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.8 auto-negotiation control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.9 crystal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.10 magnetics information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 chapter 3 setup and installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1 board configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.2 10/100base-t physical connections. . . . . . . . . . . . . . . . . . . . . .3-1 3.3 network status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 chapter 4 hardware specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.2 i/o base address and interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.3 rj-45 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 4.4 serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 4.5 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 4.6 power requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
ii
chapter publication# 22351 rev: a amendment/ 0 issue date: march 1999 1 introduction 1.1 introduction the pcnet?- fast iii board is an advanced pc network interface adapter card targeted for the fast ethernet pci adapter card market. it is based on the AM79C973 pcnet- fast iii device, a fully integrated 32-bit full-duplex, 10/100-mbps ethernet control- ler. designed to address high performance system applications, the flexible bus master architecture provides high data throughput in the system and low cpu and system bus utilization. the pcnet- fast iii board supports the pci specification (rev. 2.2), jumperless bus and media configuration, and driver software compatible with the existing pcnet family of drivers. the pcnet- fast iii board fully supports acpi/onnow power management and amds magic packet? technology. it also implements the de-facto standard 3-pin header for connecting the adapter to the power management circuitry of magic packet or wake-on-lan compliant system motherboard. this manual provides a complete description of the pcnet- fast iii board, with sections covering the functional description of each building block, the setup and installation of the board, and the hardware specification. it is assumed that the user of this manual has access to the information listed below, since references to these documents are made throughout this manual: n amd ethernet/ieee 802.3 family, 1994 world network data book/handbook (pid# 14287). n AM79C973/am79c975 pcnet-fast iii single-chip 10/100 mbps pci ethernet controller with integrated phy preliminary data sheet (pid# 21510d) n pcnet family network driver installation guide (pid# 18233e) n pci speci?cation, revision 2.2
1-2 introduction
chapter functional description 2-1 2 functional description 2.1 board description the pcnet- fast iii board is a 10/100-mbps pci network interface card. the ethernet con- nection is implemented through the single rj-45 jack which is connected to the internal 10/100 base-tx transceiver of the pcnet- fast iii device. due to the high integration of the pcnet- fast iii device, very few external parts are needed. the pcnet- fast iii eval- uation board provides the remote boot capability via an eprom or a flash device. the pcnet- fast iii evaluation card fully supports acpi/onnow power management including amds patented magic packet technology, through the lan wake-up connector. this con- nector is used to supply standby power and carry the lan wake-up signal. the connector is connected to the power management circuitry on the motherboard (if properly equipped). the following diagram illustrates the implementation of the pcnet- fast iii board. figure 2-1 board diagram 2.2 ethernet node controller the AM79C973 pcnet- fast iii ethernet controller is a fully integrated solution that con- tains a bus interface unit (biu), a dma buffer management unit, an iso/iec 8802-3 and ansi/ieee 802.3-compliant 10/100 mbps media access control (mac) and physical layer (phy) function, a ?exible buffer architecture with an sram-based fifo extension for sup- port up to 12 kbytes of internal frame buffering, optional remote boot prom/flash, and advanced power management. the integrated phy supports 10base-t, 100base-tx, and 100base-fx media interfaces. rj-45 AM79C973 pcnet- fast iii leds crystal eeprom eprom/flash socket wol transformer 22351a-1
2-2 functional description 2.3 local bus interface the pcnet- fast iii board implements the local bus interface to the peripheral compo- nents interconnect (pci) revision 2.2 speci?cation through the AM79C973 chip. the biu in the chip is designed to operate as a pci bus master during normal operations, and some slave i/o accesses to the controller are required in normal operation as well. ini- tialization of the ethernet controller is achieved through a combination of pci con?gu- ration space accesses, bus slave accesses, bus master accesses, and an optional read of a serial eeprom that is performed by the controller. 2.4 ethernet interface the ethernet interface for the pcnet- fast iii board is achieved through the single rj-45 jack. the rj-45 jack is connected through a transformer to the pcnet- fast iii controller. the transformer for the pcnet- fast iii device and board uses a 1:1.414 turns ratio for transmit (tx) and 1:1 turns ratio for receive (rx). 2.5 expansion boot rom/flash the pcnet- fast iii board can accommodate up to 1 mbyte of boot rom code. an exter- nal latch is used to allow boot rom address latching for boot rom larger than 256 kbytes. the pcnet- fast iii board supports eprom or flash as an expansion boot rom device. both are con?gured using the same methods and operate the same way. 2.6 lan wake-up connector the lan wake-up feature enables a system that is properly equipped to be awakened by a specially coded network packet. receipt of a magic packet, or a network wake-up frame, or a change in link status will awaken the system. a lan wake-up connector should be connected to the mother board with the special three-wire ribbon cable that is provided. figure 2-2 ribbon cable de?nition and recommended connectors 2.7 lan wake-up through the pme pin the pcnet- fast iii card also supports lan wake-up by the pme pin. the pme pin and 3.3 v pci auxiliary power (vaux) are new additions to the pci speci?cation, revision 2.2. in systems where the pme pin is supported, lan wake-up can be signaled by this pin. for systems that support the pme pin but do not have vaux on the pci bus/connector, the 3-pin lan wake-up cable is still needed in order to provide auxiliary power (+5 vsb) to ribbon cable amp179979-3 adapter card header amp173977-3 amp173977-3 amp179981-3 motherboard header 1 2 3 +5 vsb gnd lan wake-up 1 2 3 j1 p1 p2 j2 22351a-2
functional description 2-3 the board. if vaux is available, there is no need to use the lan wake-up cable. in this case, the board will continually be powered through vaux on the pci bus in all power states. 2.8 serial eeprom interface the pcnet- fast iii board stores the unique ieee physical address and bus con?guration of each node in the serial eeprom. once powered up, the AM79C973 chip automatically de- tects the presence of the eeprom and reads the 41 words stored in it through the microwire interface protocol. for details of the microwire interface, refer to the AM79C973 data sheet. the interface also supports the write operation to the eeprom. 2.9 auto-negotiation control the pcnet- fast iii board implements the auto-negotiation standard per the ieee 802.3 speci?cation. auto-negotiation automatically con?gures the link between two link partners through the fast link pulse. the fast link pulse is made up of a train of 17 clocks alter- nating with the 16 data ?elds for a total of 33 pulses. the two link partners send information in the 16 data positions between themselves. both sides look to see what is possible and then connect at the greatest speed and capability (without any software support) as shown in the table below. the auto-negotiation capabilities for the pcnet- fast iii board are as follows: table 2-1 auto-negotiation capabilities if the link partner is not able to auto-negotiate, the pcnet- fast iii card parallel detects the other side. this means it detects the speed correctly, but it cannot ascertain the duplex mode and reverts to half-duplex mode. 2.10 crystal information the pcnet- fast iii board uses a 25-mhz fundamental type, parallel resonant crystal with 50-100 ppm accuracy and 18 pf of capacitive load. 2.11 magnetics information the pcnet- fast iii board requires a transformer with a turns ratio of 1:1.414 (device:cable) on transmit and 1:1 on receive. table 2-2 provides an approved vendor list of magnetics recommended for use with the pcnet-fast iii device. network speed physical network type 200 mbps 100base-tx, full duplex 100 mbps 100base-tx, half duplex 20 mbps 10base-t, full duplex 10 mbps 10base-t, half duplex
2-4 functional description table 2-2 recommended magnetics vendors vendor part number package halo tg22-si43nd 16-pin module halo tg22-si41n2 16-pin module halo tg110-si41n2 16-pin module bel fuse s558-5999-g9 16-pin module bel fuse s558-5999-g8 16-pin module pulse engineering h1081 16-pin module pulse engineering h1119 16-pin module pca electronics epf8095g 16-pin module pca electronics epf8096g 16-pin module
chapter setup and installation 3-1 3 setup and installation 3.1 board configuration con?guration of the i/o base address and the interrupt channel is automatic upon power up, without any hardware jumpers. the system bios routine is responsible for assigning the i/o base address and binding the appropriate interrupt channels to the pcnet- fast iii board. 3.2 10/100base-t physical connections a data terminal equipment (dte) system with the installed pcnet- fast iii board can connect to an ethernet network using the on-board rj-45 jack for either 10base-t or 100base-tx connection. figure 3-1 illustrates a typical network con?guration for the net- work using the pcnet- fast iii board. figure 3-1 10/100base-t physical connections the auto-negotiation feature of the pcnet- fast iii controller con?gures whether the ca- pability of the network is 10 mbps or 100 mbps, and whether it is full or half-duplex. see auto-negotiation control, section 2.9. 22351a-3 8-pin rj-45 jack network hub dte twisted-pair cable dte dte
3-2 setup and installation 3.3 network status four leds on the bracket provide the network status as shown in the following table: notes: 1. valid only when led 0 is on. 2. when adapter is powered up and in operating mode, led 3 indicates a collision. when adapter is powered down or in low-power state, led 3 indicates that the controller is in magic packet mode and is ready to receive a network wake-up frame. the placement of the leds are shown in figure 3-2. figure 3-2 led placement led led 0 led 1 led 2 led 3 color green green amber green function lnkst act 10/100 ( note 1 ) col/mp ( note 2 ) meaning on = link pass off = link fail on = receive or transmit off = no activity on = 100 mbps off = 10 mbps on = collision or magic packet off = no collision led 2 led 3 led 0 led 1 22351a-4
chapter hardware speci?cations 4-1 4 hardware specifications 4.1 pci interface the AM79C973 chip on the pcnet- fast iii board contains the interface logic to the pci bus. connections to the pci bus are straightforward in that there is no external glue logic on the pcnet- fast iii board, thus making the pcnet- fast iii board fully compliant to the pci loading and trace length speci?cations. the types of pci cycles supported on the pcnet- fast iii board are as follows: n master memory read n master memory write n master memory read line n master memory read multiple n slave con?guration read n slave con?guration write n slave i/o read n slave i/o write the ?rst three types are the master cycles that the AM79C973 chip uses to transfer data across the pci bus. the AM79C973 chip owns and controls the address/data bus after its request is acknowledged by the system arbiter. if there are two or less double words to read, the AM79C973 chip uses the memory read cycle; if there are more than two double words to read, the AM79C973 chip uses the memory read line cycle. all master cycles also support the four types of slave termination schemes speci?ed in the pci re- vision 2.2 speci?cation. the last four types are the slave cycles that the host cpu uses to access con?guration and register information in the AM79C973 chip. 4.2 i/o base address and interrupt in a pci system, the i/o base address and the interrupt channel that the pcnet- fast iii board uses are assigned by the post routine. software drivers determine the i/o base address and the interrupt channel assigned to the pcnet- fast iii board by reading the pci con?guration space of the device.
4-2 hardware speci?cations table 4-1 i/o port address 4.3 rj-45 interface the pcnet- fast iii board is equipped with a rj-45 type, eight-pin modular interface. the pin con?guration and de?nition for the rj-45 connection are as follows: table 4-2 rj-45 pinout the color code may vary from one cable manufacturer to another. make sure that the tx+ and the tx- wires are twisted as a pair and the rx+ and the rx- wires are twisted as an- other pair. for 100-mbps operation, category 5 wire must be used for proper 100base-tx operation. note: do not use the telephone-type cable commonly known as silver satin (?at, with sil- ver vinyl jacket) to connect the stations as none of the wires are twisted. 4.4 serial eeprom the serial eeprom contains the ieee physical address unique to each node, the bus con?guration, and the mau con?guration information. the format of the eeprom con- tents is the following, beginning with the byte that resides at the lowest eeprom address. i/o resource access code aprom i/o base address + 0h rdp i/o base address + 10h rap i/o base address + 12h for word i/o mode (in am1500 driver compatible mode) i/o base address + 14h for double word mode reset register i/o base address + 14h for word i/o mode (in am1500 driver compatible mode) i/o base address + 1ch for double word i/o mode bdp i/o base adddres + 16h for word i/o mode (in am1500 driver compatible mode) i/o base address +1ch for double word i/o mode pin number color code function pin 1 white/orange band tx+ pin 2 orange/white band tx- pin 3 white/green band rx+ pin 6 green/white band rx- pin 4 blue/white band not used pin 5 white/blue band not used pin 7 solid orange not used pin 8 solid gray not used
hardware speci?cations 4-3 table 4-3 AM79C973 eeprom map note: *lowest eeprom address. word address byte addr most signi?cant byte byte addr least signi?cant byte 00h* 01h 2nd byte of the iso 8802-3 (ieee/ansi 802.3) station physical address for this node 00h first byte of the is0 8802-3 (ieee/ansi 802.3) station physical address for this node, where ?rst byte refers to the ?rst byte to appear on the 802.3 medium 01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h csr116[15:8] (onnow misc. con?g). 06h csr116[7:0] (onnow misc. con?g.) 04h 09h hardware id: must be 11h if compatibility to amd drivers is desired 08h reserved location: must be 00h 05h 0bh user programmable space 0ah user programmable space 06h 0dh msb of two-byte checksum, which is the sum of bytes 00h-0bh and bytes 0eh and 0fh 0ch lsb of two-byte checksum, which is the sum of bytes 00h-0bh and bytes 0eh and 0fh 07h 0fh must be ascii w (57h) if compatibility to amd driver software is desired 0eh must be ascii w (57h) if compatibility to amd driver software is desired 08h 11h bcr2[15:8] (miscellaneous con?guration) 10h bcr2[7:0] (miscellaneous con?guration) 09h 13h bcr4[15:8] (link status led) 12h bcr4[7:0] (link status led) 0ah 15h bcr5[15:8] (led1 status) 14h bcr5[7:0] (led1 status) 0bh 17h bcr6[15:8] (led2 status) 16h bcr6[7:0] (led2 status) 0ch 19h bcr7[15:8] (led3 status) 18h bcr7[7:0] (led3 status) 0dh 1bh bcr9[15:8] (full-duplex control) 1ah bcr9[7:0] (full-duplex control) 0eh 1dh bcr18[15:8] (burst and bus control) 1ch bcr18[7:0] (burst and bus control) 0fh 1fh bcr22[15:8] (pci latency) 1eh bcr22[7:0] (pci latency) 10h 21h bcr23[15:8] (pci subsystem vendor id) 20h bcr23[7:0] (pci subsystem vendor id) 11h 23h bcr24[15:8] (pci subsystem id) 22h bcr24[7:0] (pci subsystem id) 12h 25h bcr25[15:8] (sram size) 24h bcr25[7:0] (sram size) 13h 27h bcr26[15:8] (sram boundary) 26h bcr26[7:0] (sram boundary) 14h 29h bcr27[15:8] (sram interface control) 28h bcr27[7:0] (sram interface control) 15h 2bh bcr32[15:8] (mii control and status) 2ah bcr32[7:0] (mii control and status) 16h 2dh bcr33[15:8] (mii address) 2ch bcr33[7:0] (mii address) 17h 2fh bcr35[15:8] (pci vendor id) 2eh bcr35[7:0] (pci vendor id) 18h 31h bcr36[15:8] (conf. space. byte 43h alias) 30h bcr36[7:0] (conf. space byte 42h alias) 19h 33h bcr37[15:8] (data_scale alias 0) 32h bcr37[7:0] (conf. space byte 47h0alias) 1ah 35h bcr38[15:8] (data_scale alias 1) 34h bcr38[7:0] (conf. space byte 47h1alias) 1bh 37h bcr39[15:8] (data_scale alias 2) 36h bcr39[7:0] (conf. space byte 47h2alias) 1ch 39h bcr40[15:8] (data_scale alias 3) 38h bcr40[7:0] (conf. space byte 47h3alias) 1dh 3bh bcr41[15:8] (data_scale alias 4) 3ah bcr41[7:0] (conf. space byte 47h4alias) 1eh 3dh bcr42[15:8] (data_scale alias 0) 3ch bcr42[7:0] (conf. space byte 47h5alias) 1fh 3fh bcr43[15:8] (data_scale alias 0) 3eh bcr43[7:0] (conf. space byte 47h6alias) 20h 41h bcr44[15:8] (data_scale alias 0) 40h bcr44[7:0] (conf. space byte 47h7alias) 21h 43h bcr48[15:8]reserved location:must be 00h 42h bcr48[7:0]reserved location: must be 00h 22h 45h bcr49[15:8]reserved location:must be 00h 44h bcr49[7:0]reserved location: must be 00h 23h 47h bcr50[15:8]reserved location:must be 00h 46h bcr50[7:0]reserved location: must be 00h 24h 49h bcr51[15:8]reserved location:must be 00h 48h bcr51[7:0]reserved location: must be 00h 25h 4bh bcr52[15:8]reserved location:must be 00h 4ah bcr52[7:0]reserved location: must be 00h 26h 4dh bcr53[15:8]reserved location:must be 00h 4ch bcr53[7:0]reserved location: must be 00h 27h 4fh bcr54[15:8]reserved location:must be 00h 4eh bcr54[7:0]reserved location: must be 00h 28h 51h checksum adjust byte for the 82 bytes of the eeprom contents, checksum of the 82 bytes of the eeprom should total to ffh 50h bcr55[7:0]reserved location: must be 00h empty locations C ignored by device 3eh 7dh reserved for boot rom usage 7ch reserved for boot rom usage 3fh 7fh reserved for boot rom usage 7eh reserved for boot rom usage
4-4 ha r d ware speci?cations the ieee p h ysical address is unique to each node and manu f acture r . each manu f acturer of the pcnet- fast iii board must only use the address b lo c k assigned to their compa n y . amd uses 00 00 1a 18 xx xx address block. t o apply f or an ieee b lo c k addres s , the board manu f acturer must contact: ieee standard depa r tment 445 hoer lane piscat a w a y , nj 08855-1331 c/o oui registrar t el : (908) 562-3809 the eep r om contents could either be pre-programmed on an off-line eep r om program- me r , or be programmed on the pcnet- fast iii board via the microwire protocol . the ac- tual programming procedure on the off-line is left to the use r . note: the last four digits of the ieee address can be found on a label attached to the eeprom of the pcnet-fast iii board. 4.5 p h ysical dimensions without the bra c k et mounted to the board, the p h ysical dimensions of the board are as f oll o ws: n width: 4.4 inches n height: 3.2 inches 4.6 p o wer requirements the p o wer requirement of this board is 750 mw maximum at 3. 3 v dc and 25 c . t o prope r ly re?ect the p o wer consumption of the board in the pci e n vironment, the prsnt#1 and prsnt#2 signals on the boards are sho r ted to ground according to the pci r e v 2.2 speci?cation.
hardware speci?cations 4-5

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